Introduction
In previous posts I looked at programming the Si5351A clock generator with the Arduino and also examining the I2C bus (Ref.1/2/3). In this post I examine the generation of quadrature IQ signals required in modern amateur radio SDR receivers.
Quadrature IQ Signals
Quadrature signals are 90deg out of phase. The I oscillator is cos(wct) and the Q oscillator is sin(wct). Figure 1 shows cosine and sine waves along with their equivalent square waves. Clock generators typically work with PLL circuitry and produce square waves.
Si5351A Block Diagram
Figure 2 shows the essential block diagram of the Si5351A. Note there are two separate PLLs A/B with three separate output divider circuits. The VCO operates in the 600MHz to 900MHz range. A feedback divider (m + n/d) divides this frequency down and then this is compared to the reference 25MHz oscillator. The Phase Detector produces a voltage to adjust the VCO up/down in frequency until the divided frequency is exactly equal to 25MHz. There is a further divider at the output of the VCO and a final integer divider R. There are various constraints on the dividers, the primary one being that integer division is preferable to fractional division to keep the jitter down. Skyworks (purchased Silicon Labs) has a Windows based program called Clockbuilder Pro (Ref.4) that calculates the various dividers based on the Clk0/1/2 frequency choices.
AN619 (Ref.6/p.9) discusses the use of phase offset. MSx must be set to fractional dividers > 8. MSx_INT bit must be set to 0. Each LSB of the phase offset =Tvco/4, only 7 bits are available for this.
Si5351A CLK0 & CLK1 90deg Phase Shift Example 14.1MHz
Arduino has a library “Etherkit Si5351” which you can install. Figure 4 shows the file si5351_phase.ino that can be used to demonstrate a 90deg phase shift between two clocks at 14.1MHz. The two outputs have to be referenced to the same PLL and be at the same frequency. I adjusted the .cpp driver file for Reg16/17 from $0c to $0f to get the full 8mA drive consistent with my previous posts.
Si5351A CLK0 & CLK1 90deg Phase Shift 21.0946MHz
We can modify the si5351_phase.ino code for a different frequency. Let’s pick the 15m WSPR frequency of 21.0946MHz. In order to get a 90deg phase shift, you pick the output divider to be an even integer such that (21.0946MHz * divider) falls within the PLLA range. The reason we pick an even integer is so that the number of clock phase shift LSBs = divider which gives us exactly 90deg shift (AN619 p.9). If we choose the divider as say 30, then we have the following:
div=30
PLLA=21.0946*30=632.838MHz
m=25
n=31352
d=100000
div=30
n=0
d=1
CLK0=21.0946MHz 0nsec
CLK1=21.0946MHz +11.85nsec
Figure 7/8 shows the modified code, and Figures 9/10 shows the CLK0/1 outputs and spectra.
Please send your comments, questions and suggestions to:
contact:
References
#1. – “Si5351 Clock Generator I2C”
https://jeremyclark.ca/wp/telecom/si5351-clock-generator-i2c/
#2. – “Si5351 Clock Generator Programming+”
https://jeremyclark.ca/wp/telecom/si5351-clock-generator-programming-2/
#3. – “Si5351 Clock Generator Programming”
https://jeremyclark.ca/wp/telecom/si5351-clock-generator-programming/
#4. – “ClockBuilderPro”
https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software
#5. – “Si5351A Data Sheet”
https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5351-B.pdf
#6. – “AN619 Si5352 Register Map”
https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/application-notes/AN619.pdf
